The explorer is out of sync. The last synced block is 568 hours ago. Current block height: explorer: 2206528 / node: 2569353 / ref: 2492275
program interest_m3tlfwm.aleo; function fixed_iteration_interest: input r0 as u32.private; input r1 as u32.public; mul r0 r1 into r2; div r2 100u32 into r3; add r0 r3 into r4; mul r4 r1 into r5; div r5 100u32 into r6; add r4 r6 into r7; mul r7 r1 into r8; div r8 100u32 into r9; add r7 r9 into r10; mul r10 r1 into r11; div r11 100u32 into r12; add r10 r12 into r13; mul r13 r1 into r14; div r14 100u32 into r15; add r13 r15 into r16; mul r16 r1 into r17; div r17 100u32 into r18; add r16 r18 into r19; mul r19 r1 into r20; div r20 100u32 into r21; add r19 r21 into r22; mul r22 r1 into r23; div r23 100u32 into r24; add r22 r24 into r25; mul r25 r1 into r26; div r26 100u32 into r27; add r25 r27 into r28; mul r28 r1 into r29; div r29 100u32 into r30; add r28 r30 into r31; output r31 as u32.private; function bounded_iteration_interest: input r0 as u32.private; input r1 as u32.public; input r2 as u8.private; lte r2 50u8 into r3; assert.eq r3 true; lt 0u8 r2 into r4; mul r0 r1 into r5; div r5 100u32 into r6; add r0 r6 into r7; ternary r4 r7 r0 into r8; is.eq 0u8 40u8 into r9; lt 1u8 r2 into r10; mul r8 r1 into r11; div r11 100u32 into r12; add r8 r12 into r13; ternary r10 r13 r8 into r14; is.eq 1u8 40u8 into r15; lt 2u8 r2 into r16; mul r14 r1 into r17; div r17 100u32 into r18; add r14 r18 into r19; ternary r16 r19 r14 into r20; is.eq 2u8 40u8 into r21; lt 3u8 r2 into r22; mul r20 r1 into r23; div r23 100u32 into r24; add r20 r24 into r25; ternary r22 r25 r20 into r26; is.eq 3u8 40u8 into r27; lt 4u8 r2 into r28; mul r26 r1 into r29; div r29 100u32 into r30; add r26 r30 into r31; ternary r28 r31 r26 into r32; is.eq 4u8 40u8 into r33; lt 5u8 r2 into r34; mul r32 r1 into r35; div r35 100u32 into r36; add r32 r36 into r37; ternary r34 r37 r32 into r38; is.eq 5u8 40u8 into r39; lt 6u8 r2 into r40; mul r38 r1 into r41; div r41 100u32 into r42; add r38 r42 into r43; ternary r40 r43 r38 into r44; is.eq 6u8 40u8 into r45; lt 7u8 r2 into r46; mul r44 r1 into r47; div r47 100u32 into r48; add r44 r48 into r49; ternary r46 r49 r44 into r50; is.eq 7u8 40u8 into r51; lt 8u8 r2 into r52; mul r50 r1 into r53; div r53 100u32 into r54; add r50 r54 into r55; ternary r52 r55 r50 into r56; is.eq 8u8 40u8 into r57; lt 9u8 r2 into r58; mul r56 r1 into r59; div r59 100u32 into r60; add r56 r60 into r61; ternary r58 r61 r56 into r62; is.eq 9u8 40u8 into r63; lt 10u8 r2 into r64; mul r62 r1 into r65; div r65 100u32 into r66; add r62 r66 into r67; ternary r64 r67 r62 into r68; is.eq 10u8 40u8 into r69; lt 11u8 r2 into r70; mul r68 r1 into r71; div r71 100u32 into r72; add r68 r72 into r73; ternary r70 r73 r68 into r74; is.eq 11u8 40u8 into r75; lt 12u8 r2 into r76; mul r74 r1 into r77; div r77 100u32 into r78; add r74 r78 into r79; ternary r76 r79 r74 into r80; is.eq 12u8 40u8 into r81; lt 13u8 r2 into r82; mul r80 r1 into r83; div r83 100u32 into r84; add r80 r84 into r85; ternary r82 r85 r80 into r86; is.eq 13u8 40u8 into r87; lt 14u8 r2 into r88; mul r86 r1 into r89; div r89 100u32 into r90; add r86 r90 into r91; ternary r88 r91 r86 into r92; is.eq 14u8 40u8 into r93; lt 15u8 r2 into r94; mul r92 r1 into r95; div r95 100u32 into r96; add r92 r96 into r97; ternary r94 r97 r92 into r98; is.eq 15u8 40u8 into r99; lt 16u8 r2 into r100; mul r98 r1 into r101; div r101 100u32 into r102; add r98 r102 into r103; ternary r100 r103 r98 into r104; is.eq 16u8 40u8 into r105; lt 17u8 r2 into r106; mul r104 r1 into r107; div r107 100u32 into r108; add r104 r108 into r109; ternary r106 r109 r104 into r110; is.eq 17u8 40u8 into r111; lt 18u8 r2 into r112; mul r110 r1 into r113; div r113 100u32 into r114; add r110 r114 into r115; ternary r112 r115 r110 into r116; is.eq 18u8 40u8 into r117; lt 19u8 r2 into r118; mul r116 r1 into r119; div r119 100u32 into r120; add r116 r120 into r121; ternary r118 r121 r116 into r122; is.eq 19u8 40u8 into r123; lt 20u8 r2 into r124; mul r122 r1 into r125; div r125 100u32 into r126; add r122 r126 into r127; ternary r124 r127 r122 into r128; is.eq 20u8 40u8 into r129; lt 21u8 r2 into r130; mul r128 r1 into r131; div r131 100u32 into r132; add r128 r132 into r133; ternary r130 r133 r128 into r134; is.eq 21u8 40u8 into r135; lt 22u8 r2 into r136; mul r134 r1 into r137; div r137 100u32 into r138; add r134 r138 into r139; ternary r136 r139 r134 into r140; is.eq 22u8 40u8 into r141; lt 23u8 r2 into r142; mul r140 r1 into r143; div r143 100u32 into r144; add r140 r144 into r145; ternary r142 r145 r140 into r146; is.eq 23u8 40u8 into r147; lt 24u8 r2 into r148; mul r146 r1 into r149; div r149 100u32 into r150; add r146 r150 into r151; ternary r148 r151 r146 into r152; is.eq 24u8 40u8 into r153; lt 25u8 r2 into r154; mul r152 r1 into r155; div r155 100u32 into r156; add r152 r156 into r157; ternary r154 r157 r152 into r158; is.eq 25u8 40u8 into r159; lt 26u8 r2 into r160; mul r158 r1 into r161; div r161 100u32 into r162; add r158 r162 into r163; ternary r160 r163 r158 into r164; is.eq 26u8 40u8 into r165; lt 27u8 r2 into r166; mul r164 r1 into r167; div r167 100u32 into r168; add r164 r168 into r169; ternary r166 r169 r164 into r170; is.eq 27u8 40u8 into r171; lt 28u8 r2 into r172; mul r170 r1 into r173; div r173 100u32 into r174; add r170 r174 into r175; ternary r172 r175 r170 into r176; is.eq 28u8 40u8 into r177; lt 29u8 r2 into r178; mul r176 r1 into r179; div r179 100u32 into r180; add r176 r180 into r181; ternary r178 r181 r176 into r182; is.eq 29u8 40u8 into r183; lt 30u8 r2 into r184; mul r182 r1 into r185; div r185 100u32 into r186; add r182 r186 into r187; ternary r184 r187 r182 into r188; is.eq 30u8 40u8 into r189; lt 31u8 r2 into r190; mul r188 r1 into r191; div r191 100u32 into r192; add r188 r192 into r193; ternary r190 r193 r188 into r194; is.eq 31u8 40u8 into r195; lt 32u8 r2 into r196; mul r194 r1 into r197; div r197 100u32 into r198; add r194 r198 into r199; ternary r196 r199 r194 into r200; is.eq 32u8 40u8 into r201; lt 33u8 r2 into r202; mul r200 r1 into r203; div r203 100u32 into r204; add r200 r204 into r205; ternary r202 r205 r200 into r206; is.eq 33u8 40u8 into r207; lt 34u8 r2 into r208; mul r206 r1 into r209; div r209 100u32 into r210; add r206 r210 into r211; ternary r208 r211 r206 into r212; is.eq 34u8 40u8 into r213; lt 35u8 r2 into r214; mul r212 r1 into r215; div r215 100u32 into r216; add r212 r216 into r217; ternary r214 r217 r212 into r218; is.eq 35u8 40u8 into r219; lt 36u8 r2 into r220; mul r218 r1 into r221; div r221 100u32 into r222; add r218 r222 into r223; ternary r220 r223 r218 into r224; is.eq 36u8 40u8 into r225; lt 37u8 r2 into r226; mul r224 r1 into r227; div r227 100u32 into r228; add r224 r228 into r229; ternary r226 r229 r224 into r230; is.eq 37u8 40u8 into r231; lt 38u8 r2 into r232; mul r230 r1 into r233; div r233 100u32 into r234; add r230 r234 into r235; ternary r232 r235 r230 into r236; is.eq 38u8 40u8 into r237; lt 39u8 r2 into r238; mul r236 r1 into r239; div r239 100u32 into r240; add r236 r240 into r241; ternary r238 r241 r236 into r242; is.eq 39u8 40u8 into r243; lt 40u8 r2 into r244; mul r242 r1 into r245; div r245 100u32 into r246; add r242 r246 into r247; ternary r244 r247 r242 into r248; is.eq 40u8 40u8 into r249; lt 41u8 r2 into r250; mul r248 r1 into r251; div r251 100u32 into r252; add r248 r252 into r253; ternary r250 r253 r248 into r254; is.eq 41u8 40u8 into r255; lt 42u8 r2 into r256; mul r254 r1 into r257; div r257 100u32 into r258; add r254 r258 into r259; ternary r256 r259 r254 into r260; is.eq 42u8 40u8 into r261; lt 43u8 r2 into r262; mul r260 r1 into r263; div r263 100u32 into r264; add r260 r264 into r265; ternary r262 r265 r260 into r266; is.eq 43u8 40u8 into r267; lt 44u8 r2 into r268; mul r266 r1 into r269; div r269 100u32 into r270; add r266 r270 into r271; ternary r268 r271 r266 into r272; is.eq 44u8 40u8 into r273; lt 45u8 r2 into r274; mul r272 r1 into r275; div r275 100u32 into r276; add r272 r276 into r277; ternary r274 r277 r272 into r278; is.eq 45u8 40u8 into r279; lt 46u8 r2 into r280; mul r278 r1 into r281; div r281 100u32 into r282; add r278 r282 into r283; ternary r280 r283 r278 into r284; is.eq 46u8 40u8 into r285; lt 47u8 r2 into r286; mul r284 r1 into r287; div r287 100u32 into r288; add r284 r288 into r289; ternary r286 r289 r284 into r290; is.eq 47u8 40u8 into r291; lt 48u8 r2 into r292; mul r290 r1 into r293; div r293 100u32 into r294; add r290 r294 into r295; ternary r292 r295 r290 into r296; is.eq 48u8 40u8 into r297; lt 49u8 r2 into r298; mul r296 r1 into r299; div r299 100u32 into r300; add r296 r300 into r301; ternary r298 r301 r296 into r302; is.eq 49u8 40u8 into r303; ternary r303 r302 r302 into r304; ternary r297 r296 r304 into r305; ternary r291 r290 r305 into r306; ternary r285 r284 r306 into r307; ternary r279 r278 r307 into r308; ternary r273 r272 r308 into r309; ternary r267 r266 r309 into r310; ternary r261 r260 r310 into r311; ternary r255 r254 r311 into r312; ternary r249 r248 r312 into r313; ternary r243 r242 r313 into r314; ternary r237 r236 r314 into r315; ternary r231 r230 r315 into r316; ternary r225 r224 r316 into r317; ternary r219 r218 r317 into r318; ternary r213 r212 r318 into r319; ternary r207 r206 r319 into r320; ternary r201 r200 r320 into r321; ternary r195 r194 r321 into r322; ternary r189 r188 r322 into r323; ternary r183 r182 r323 into r324; ternary r177 r176 r324 into r325; ternary r171 r170 r325 into r326; ternary r165 r164 r326 into r327; ternary r159 r158 r327 into r328; ternary r153 r152 r328 into r329; ternary r147 r146 r329 into r330; ternary r141 r140 r330 into r331; ternary r135 r134 r331 into r332; ternary r129 r128 r332 into r333; ternary r123 r122 r333 into r334; ternary r117 r116 r334 into r335; ternary r111 r110 r335 into r336; ternary r105 r104 r336 into r337; ternary r99 r98 r337 into r338; ternary r93 r92 r338 into r339; ternary r87 r86 r339 into r340; ternary r81 r80 r340 into r341; ternary r75 r74 r341 into r342; ternary r69 r68 r342 into r343; ternary r63 r62 r343 into r344; ternary r57 r56 r344 into r345; ternary r51 r50 r345 into r346; ternary r45 r44 r346 into r347; ternary r39 r38 r347 into r348; ternary r33 r32 r348 into r349; ternary r27 r26 r349 into r350; ternary r21 r20 r350 into r351; ternary r15 r14 r351 into r352; ternary r9 r8 r352 into r353; output r353 as u32.private;
Block height | Timestamp | Transition ID | Function call | State |