program bank_whoru.aleo;

record Token:
    owner as address.private;
    amount as u64.private;

mapping balances:
    key as field.public;
    value as u64.public;

function issue:
    input r0 as address.private;
    input r1 as u64.private;
    cast r0 r1 into r2 as Token.record;
    output r2 as Token.record;

function deposit:
    input r0 as Token.record;
    input r1 as u64.private;
    sub r0.amount r1 into r2;
    cast r0.owner r2 into r3 as Token.record;
    hash.bhp256 r0.owner into r4 as field;
    async deposit r4 r1 into r5;
    output r3 as Token.record;
    output r5 as bank_whoru.aleo/deposit.future;
finalize deposit:
    input r0 as field.public;
    input r1 as u64.public;
    get.or_use balances[r0] 0u64 into r2;
    add r2 r1 into r3;
    set r3 into balances[r0];

closure calculate_interest:
    input r0 as u64;
    input r1 as u64;
    input r2 as u64;
    lt 0u64 r2 into r3;
    mul r0 r1 into r4;
    div r4 10000u64 into r5;
    add r0 r5 into r6;
    ternary r3 r6 r0 into r7;
    lt 1u64 r2 into r8;
    mul r7 r1 into r9;
    div r9 10000u64 into r10;
    add r7 r10 into r11;
    ternary r8 r11 r7 into r12;
    lt 2u64 r2 into r13;
    mul r12 r1 into r14;
    div r14 10000u64 into r15;
    add r12 r15 into r16;
    ternary r13 r16 r12 into r17;
    lt 3u64 r2 into r18;
    mul r17 r1 into r19;
    div r19 10000u64 into r20;
    add r17 r20 into r21;
    ternary r18 r21 r17 into r22;
    lt 4u64 r2 into r23;
    mul r22 r1 into r24;
    div r24 10000u64 into r25;
    add r22 r25 into r26;
    ternary r23 r26 r22 into r27;
    lt 5u64 r2 into r28;
    mul r27 r1 into r29;
    div r29 10000u64 into r30;
    add r27 r30 into r31;
    ternary r28 r31 r27 into r32;
    lt 6u64 r2 into r33;
    mul r32 r1 into r34;
    div r34 10000u64 into r35;
    add r32 r35 into r36;
    ternary r33 r36 r32 into r37;
    lt 7u64 r2 into r38;
    mul r37 r1 into r39;
    div r39 10000u64 into r40;
    add r37 r40 into r41;
    ternary r38 r41 r37 into r42;
    lt 8u64 r2 into r43;
    mul r42 r1 into r44;
    div r44 10000u64 into r45;
    add r42 r45 into r46;
    ternary r43 r46 r42 into r47;
    lt 9u64 r2 into r48;
    mul r47 r1 into r49;
    div r49 10000u64 into r50;
    add r47 r50 into r51;
    ternary r48 r51 r47 into r52;
    lt 10u64 r2 into r53;
    mul r52 r1 into r54;
    div r54 10000u64 into r55;
    add r52 r55 into r56;
    ternary r53 r56 r52 into r57;
    lt 11u64 r2 into r58;
    mul r57 r1 into r59;
    div r59 10000u64 into r60;
    add r57 r60 into r61;
    ternary r58 r61 r57 into r62;
    lt 12u64 r2 into r63;
    mul r62 r1 into r64;
    div r64 10000u64 into r65;
    add r62 r65 into r66;
    ternary r63 r66 r62 into r67;
    lt 13u64 r2 into r68;
    mul r67 r1 into r69;
    div r69 10000u64 into r70;
    add r67 r70 into r71;
    ternary r68 r71 r67 into r72;
    lt 14u64 r2 into r73;
    mul r72 r1 into r74;
    div r74 10000u64 into r75;
    add r72 r75 into r76;
    ternary r73 r76 r72 into r77;
    lt 15u64 r2 into r78;
    mul r77 r1 into r79;
    div r79 10000u64 into r80;
    add r77 r80 into r81;
    ternary r78 r81 r77 into r82;
    lt 16u64 r2 into r83;
    mul r82 r1 into r84;
    div r84 10000u64 into r85;
    add r82 r85 into r86;
    ternary r83 r86 r82 into r87;
    lt 17u64 r2 into r88;
    mul r87 r1 into r89;
    div r89 10000u64 into r90;
    add r87 r90 into r91;
    ternary r88 r91 r87 into r92;
    lt 18u64 r2 into r93;
    mul r92 r1 into r94;
    div r94 10000u64 into r95;
    add r92 r95 into r96;
    ternary r93 r96 r92 into r97;
    lt 19u64 r2 into r98;
    mul r97 r1 into r99;
    div r99 10000u64 into r100;
    add r97 r100 into r101;
    ternary r98 r101 r97 into r102;
    lt 20u64 r2 into r103;
    mul r102 r1 into r104;
    div r104 10000u64 into r105;
    add r102 r105 into r106;
    ternary r103 r106 r102 into r107;
    lt 21u64 r2 into r108;
    mul r107 r1 into r109;
    div r109 10000u64 into r110;
    add r107 r110 into r111;
    ternary r108 r111 r107 into r112;
    lt 22u64 r2 into r113;
    mul r112 r1 into r114;
    div r114 10000u64 into r115;
    add r112 r115 into r116;
    ternary r113 r116 r112 into r117;
    lt 23u64 r2 into r118;
    mul r117 r1 into r119;
    div r119 10000u64 into r120;
    add r117 r120 into r121;
    ternary r118 r121 r117 into r122;
    lt 24u64 r2 into r123;
    mul r122 r1 into r124;
    div r124 10000u64 into r125;
    add r122 r125 into r126;
    ternary r123 r126 r122 into r127;
    lt 25u64 r2 into r128;
    mul r127 r1 into r129;
    div r129 10000u64 into r130;
    add r127 r130 into r131;
    ternary r128 r131 r127 into r132;
    lt 26u64 r2 into r133;
    mul r132 r1 into r134;
    div r134 10000u64 into r135;
    add r132 r135 into r136;
    ternary r133 r136 r132 into r137;
    lt 27u64 r2 into r138;
    mul r137 r1 into r139;
    div r139 10000u64 into r140;
    add r137 r140 into r141;
    ternary r138 r141 r137 into r142;
    lt 28u64 r2 into r143;
    mul r142 r1 into r144;
    div r144 10000u64 into r145;
    add r142 r145 into r146;
    ternary r143 r146 r142 into r147;
    lt 29u64 r2 into r148;
    mul r147 r1 into r149;
    div r149 10000u64 into r150;
    add r147 r150 into r151;
    ternary r148 r151 r147 into r152;
    lt 30u64 r2 into r153;
    mul r152 r1 into r154;
    div r154 10000u64 into r155;
    add r152 r155 into r156;
    ternary r153 r156 r152 into r157;
    lt 31u64 r2 into r158;
    mul r157 r1 into r159;
    div r159 10000u64 into r160;
    add r157 r160 into r161;
    ternary r158 r161 r157 into r162;
    lt 32u64 r2 into r163;
    mul r162 r1 into r164;
    div r164 10000u64 into r165;
    add r162 r165 into r166;
    ternary r163 r166 r162 into r167;
    lt 33u64 r2 into r168;
    mul r167 r1 into r169;
    div r169 10000u64 into r170;
    add r167 r170 into r171;
    ternary r168 r171 r167 into r172;
    lt 34u64 r2 into r173;
    mul r172 r1 into r174;
    div r174 10000u64 into r175;
    add r172 r175 into r176;
    ternary r173 r176 r172 into r177;
    lt 35u64 r2 into r178;
    mul r177 r1 into r179;
    div r179 10000u64 into r180;
    add r177 r180 into r181;
    ternary r178 r181 r177 into r182;
    lt 36u64 r2 into r183;
    mul r182 r1 into r184;
    div r184 10000u64 into r185;
    add r182 r185 into r186;
    ternary r183 r186 r182 into r187;
    lt 37u64 r2 into r188;
    mul r187 r1 into r189;
    div r189 10000u64 into r190;
    add r187 r190 into r191;
    ternary r188 r191 r187 into r192;
    lt 38u64 r2 into r193;
    mul r192 r1 into r194;
    div r194 10000u64 into r195;
    add r192 r195 into r196;
    ternary r193 r196 r192 into r197;
    lt 39u64 r2 into r198;
    mul r197 r1 into r199;
    div r199 10000u64 into r200;
    add r197 r200 into r201;
    ternary r198 r201 r197 into r202;
    lt 40u64 r2 into r203;
    mul r202 r1 into r204;
    div r204 10000u64 into r205;
    add r202 r205 into r206;
    ternary r203 r206 r202 into r207;
    lt 41u64 r2 into r208;
    mul r207 r1 into r209;
    div r209 10000u64 into r210;
    add r207 r210 into r211;
    ternary r208 r211 r207 into r212;
    lt 42u64 r2 into r213;
    mul r212 r1 into r214;
    div r214 10000u64 into r215;
    add r212 r215 into r216;
    ternary r213 r216 r212 into r217;
    lt 43u64 r2 into r218;
    mul r217 r1 into r219;
    div r219 10000u64 into r220;
    add r217 r220 into r221;
    ternary r218 r221 r217 into r222;
    lt 44u64 r2 into r223;
    mul r222 r1 into r224;
    div r224 10000u64 into r225;
    add r222 r225 into r226;
    ternary r223 r226 r222 into r227;
    lt 45u64 r2 into r228;
    mul r227 r1 into r229;
    div r229 10000u64 into r230;
    add r227 r230 into r231;
    ternary r228 r231 r227 into r232;
    lt 46u64 r2 into r233;
    mul r232 r1 into r234;
    div r234 10000u64 into r235;
    add r232 r235 into r236;
    ternary r233 r236 r232 into r237;
    lt 47u64 r2 into r238;
    mul r237 r1 into r239;
    div r239 10000u64 into r240;
    add r237 r240 into r241;
    ternary r238 r241 r237 into r242;
    lt 48u64 r2 into r243;
    mul r242 r1 into r244;
    div r244 10000u64 into r245;
    add r242 r245 into r246;
    ternary r243 r246 r242 into r247;
    lt 49u64 r2 into r248;
    mul r247 r1 into r249;
    div r249 10000u64 into r250;
    add r247 r250 into r251;
    ternary r248 r251 r247 into r252;
    lt 50u64 r2 into r253;
    mul r252 r1 into r254;
    div r254 10000u64 into r255;
    add r252 r255 into r256;
    ternary r253 r256 r252 into r257;
    lt 51u64 r2 into r258;
    mul r257 r1 into r259;
    div r259 10000u64 into r260;
    add r257 r260 into r261;
    ternary r258 r261 r257 into r262;
    lt 52u64 r2 into r263;
    mul r262 r1 into r264;
    div r264 10000u64 into r265;
    add r262 r265 into r266;
    ternary r263 r266 r262 into r267;
    lt 53u64 r2 into r268;
    mul r267 r1 into r269;
    div r269 10000u64 into r270;
    add r267 r270 into r271;
    ternary r268 r271 r267 into r272;
    lt 54u64 r2 into r273;
    mul r272 r1 into r274;
    div r274 10000u64 into r275;
    add r272 r275 into r276;
    ternary r273 r276 r272 into r277;
    lt 55u64 r2 into r278;
    mul r277 r1 into r279;
    div r279 10000u64 into r280;
    add r277 r280 into r281;
    ternary r278 r281 r277 into r282;
    lt 56u64 r2 into r283;
    mul r282 r1 into r284;
    div r284 10000u64 into r285;
    add r282 r285 into r286;
    ternary r283 r286 r282 into r287;
    lt 57u64 r2 into r288;
    mul r287 r1 into r289;
    div r289 10000u64 into r290;
    add r287 r290 into r291;
    ternary r288 r291 r287 into r292;
    lt 58u64 r2 into r293;
    mul r292 r1 into r294;
    div r294 10000u64 into r295;
    add r292 r295 into r296;
    ternary r293 r296 r292 into r297;
    lt 59u64 r2 into r298;
    mul r297 r1 into r299;
    div r299 10000u64 into r300;
    add r297 r300 into r301;
    ternary r298 r301 r297 into r302;
    lt 60u64 r2 into r303;
    mul r302 r1 into r304;
    div r304 10000u64 into r305;
    add r302 r305 into r306;
    ternary r303 r306 r302 into r307;
    lt 61u64 r2 into r308;
    mul r307 r1 into r309;
    div r309 10000u64 into r310;
    add r307 r310 into r311;
    ternary r308 r311 r307 into r312;
    lt 62u64 r2 into r313;
    mul r312 r1 into r314;
    div r314 10000u64 into r315;
    add r312 r315 into r316;
    ternary r313 r316 r312 into r317;
    lt 63u64 r2 into r318;
    mul r317 r1 into r319;
    div r319 10000u64 into r320;
    add r317 r320 into r321;
    ternary r318 r321 r317 into r322;
    lt 64u64 r2 into r323;
    mul r322 r1 into r324;
    div r324 10000u64 into r325;
    add r322 r325 into r326;
    ternary r323 r326 r322 into r327;
    lt 65u64 r2 into r328;
    mul r327 r1 into r329;
    div r329 10000u64 into r330;
    add r327 r330 into r331;
    ternary r328 r331 r327 into r332;
    lt 66u64 r2 into r333;
    mul r332 r1 into r334;
    div r334 10000u64 into r335;
    add r332 r335 into r336;
    ternary r333 r336 r332 into r337;
    lt 67u64 r2 into r338;
    mul r337 r1 into r339;
    div r339 10000u64 into r340;
    add r337 r340 into r341;
    ternary r338 r341 r337 into r342;
    lt 68u64 r2 into r343;
    mul r342 r1 into r344;
    div r344 10000u64 into r345;
    add r342 r345 into r346;
    ternary r343 r346 r342 into r347;
    lt 69u64 r2 into r348;
    mul r347 r1 into r349;
    div r349 10000u64 into r350;
    add r347 r350 into r351;
    ternary r348 r351 r347 into r352;
    lt 70u64 r2 into r353;
    mul r352 r1 into r354;
    div r354 10000u64 into r355;
    add r352 r355 into r356;
    ternary r353 r356 r352 into r357;
    lt 71u64 r2 into r358;
    mul r357 r1 into r359;
    div r359 10000u64 into r360;
    add r357 r360 into r361;
    ternary r358 r361 r357 into r362;
    lt 72u64 r2 into r363;
    mul r362 r1 into r364;
    div r364 10000u64 into r365;
    add r362 r365 into r366;
    ternary r363 r366 r362 into r367;
    lt 73u64 r2 into r368;
    mul r367 r1 into r369;
    div r369 10000u64 into r370;
    add r367 r370 into r371;
    ternary r368 r371 r367 into r372;
    lt 74u64 r2 into r373;
    mul r372 r1 into r374;
    div r374 10000u64 into r375;
    add r372 r375 into r376;
    ternary r373 r376 r372 into r377;
    lt 75u64 r2 into r378;
    mul r377 r1 into r379;
    div r379 10000u64 into r380;
    add r377 r380 into r381;
    ternary r378 r381 r377 into r382;
    lt 76u64 r2 into r383;
    mul r382 r1 into r384;
    div r384 10000u64 into r385;
    add r382 r385 into r386;
    ternary r383 r386 r382 into r387;
    lt 77u64 r2 into r388;
    mul r387 r1 into r389;
    div r389 10000u64 into r390;
    add r387 r390 into r391;
    ternary r388 r391 r387 into r392;
    lt 78u64 r2 into r393;
    mul r392 r1 into r394;
    div r394 10000u64 into r395;
    add r392 r395 into r396;
    ternary r393 r396 r392 into r397;
    lt 79u64 r2 into r398;
    mul r397 r1 into r399;
    div r399 10000u64 into r400;
    add r397 r400 into r401;
    ternary r398 r401 r397 into r402;
    lt 80u64 r2 into r403;
    mul r402 r1 into r404;
    div r404 10000u64 into r405;
    add r402 r405 into r406;
    ternary r403 r406 r402 into r407;
    lt 81u64 r2 into r408;
    mul r407 r1 into r409;
    div r409 10000u64 into r410;
    add r407 r410 into r411;
    ternary r408 r411 r407 into r412;
    lt 82u64 r2 into r413;
    mul r412 r1 into r414;
    div r414 10000u64 into r415;
    add r412 r415 into r416;
    ternary r413 r416 r412 into r417;
    lt 83u64 r2 into r418;
    mul r417 r1 into r419;
    div r419 10000u64 into r420;
    add r417 r420 into r421;
    ternary r418 r421 r417 into r422;
    lt 84u64 r2 into r423;
    mul r422 r1 into r424;
    div r424 10000u64 into r425;
    add r422 r425 into r426;
    ternary r423 r426 r422 into r427;
    lt 85u64 r2 into r428;
    mul r427 r1 into r429;
    div r429 10000u64 into r430;
    add r427 r430 into r431;
    ternary r428 r431 r427 into r432;
    lt 86u64 r2 into r433;
    mul r432 r1 into r434;
    div r434 10000u64 into r435;
    add r432 r435 into r436;
    ternary r433 r436 r432 into r437;
    lt 87u64 r2 into r438;
    mul r437 r1 into r439;
    div r439 10000u64 into r440;
    add r437 r440 into r441;
    ternary r438 r441 r437 into r442;
    lt 88u64 r2 into r443;
    mul r442 r1 into r444;
    div r444 10000u64 into r445;
    add r442 r445 into r446;
    ternary r443 r446 r442 into r447;
    lt 89u64 r2 into r448;
    mul r447 r1 into r449;
    div r449 10000u64 into r450;
    add r447 r450 into r451;
    ternary r448 r451 r447 into r452;
    lt 90u64 r2 into r453;
    mul r452 r1 into r454;
    div r454 10000u64 into r455;
    add r452 r455 into r456;
    ternary r453 r456 r452 into r457;
    lt 91u64 r2 into r458;
    mul r457 r1 into r459;
    div r459 10000u64 into r460;
    add r457 r460 into r461;
    ternary r458 r461 r457 into r462;
    lt 92u64 r2 into r463;
    mul r462 r1 into r464;
    div r464 10000u64 into r465;
    add r462 r465 into r466;
    ternary r463 r466 r462 into r467;
    lt 93u64 r2 into r468;
    mul r467 r1 into r469;
    div r469 10000u64 into r470;
    add r467 r470 into r471;
    ternary r468 r471 r467 into r472;
    lt 94u64 r2 into r473;
    mul r472 r1 into r474;
    div r474 10000u64 into r475;
    add r472 r475 into r476;
    ternary r473 r476 r472 into r477;
    lt 95u64 r2 into r478;
    mul r477 r1 into r479;
    div r479 10000u64 into r480;
    add r477 r480 into r481;
    ternary r478 r481 r477 into r482;
    lt 96u64 r2 into r483;
    mul r482 r1 into r484;
    div r484 10000u64 into r485;
    add r482 r485 into r486;
    ternary r483 r486 r482 into r487;
    lt 97u64 r2 into r488;
    mul r487 r1 into r489;
    div r489 10000u64 into r490;
    add r487 r490 into r491;
    ternary r488 r491 r487 into r492;
    lt 98u64 r2 into r493;
    mul r492 r1 into r494;
    div r494 10000u64 into r495;
    add r492 r495 into r496;
    ternary r493 r496 r492 into r497;
    lt 99u64 r2 into r498;
    mul r497 r1 into r499;
    div r499 10000u64 into r500;
    add r497 r500 into r501;
    ternary r498 r501 r497 into r502;
    output r502 as u64;

function withdraw:
    input r0 as address.private;
    input r1 as u64.private;
    input r2 as u64.private;
    input r3 as u64.private;
    hash.bhp256 r0 into r4 as field;
    call calculate_interest r1 r2 r3 into r5;
    cast r0 r5 into r6 as Token.record;
    async withdraw r4 r1 into r7;
    output r6 as Token.record;
    output r7 as bank_whoru.aleo/withdraw.future;
finalize withdraw:
    input r0 as field.public;
    input r1 as u64.public;
    get.or_use balances[r0] 0u64 into r2;
    sub r2 r1 into r3;
    set r3 into balances[r0];

Not implemented